One-Day Workshop on VLSI Design Flow

Participants being guided through Tanner-based Verilog A coding by Mrs. Anu Sasindran.
  • August 11, 2017
  • College of Engineering, Chengannur

One day workshop on “VLSI Design Flow” was organized by SSCS Chapter and IEDC Boot Camp College of Engineering Chengannur, India on 11th August 2017. The workshop was attended by B.Tech as well as PG students in the college. The aim of the programme was to introduce the participants to the world of VLSI design, and to provide a platform for the recently graduated students to share the knowledge they acquired to the current students.

The event began with a prayer at 9.30am and Dr. Nisha Kuruvilla, SSCS Chapter Advisor, College of Engineering Chengannur delivered a comprehensive introduction speech about the workshop. Mr. Ayoob Khan, Associate Professor, College of Engineering officially inaugurated the programme.

The first session on “Introduction to Tanner EDA: Schematic and Layout Design” was led by Ms. Sreelekshmi P.S., a former post graduate of the college. She gave an introduction about the significance of EDA tools and gave a hands on workshop on Tanner EDA tool. This involved guiding the participants through making a schematic of basic MOS circuit and their layout design. After a short break, the session continued, this time led by Mrs. Anu Sasindran, also a former graduate, who spoke about Verilog A coding in Tanner EDA. The session ended on 1.30pm.

The second session started at 2pm after the lunch break and it was led by Mr. Subin Abraham, former graduate of the college. It was a hand on training on FPGA implementation. The participants were introduced to VHDL coding of basic circuits and their implementation on an FPGA kit. The session ended at 3.45pm.

Prof. Dr. Jyothiraj V.P., the Head of Department, Electronics and Communication, awarded the resource persons with certificates and cash prize. He congratulated them for their successful journey as students and wished them good luck in future endeavors.

Tanner EDA Schematic Design workshop by Ms. Sreelekshmi P.S.
Tanner EDA Schematic Design workshop by Ms. Sreelekshmi P.S.
FPGA Implementation workshop by Mr. Subin Abraham.
FPGA Implementation workshop by Mr. Subin Abraham.
Resource person being awarded certificate by Dr. Jyothiraj V.P., Head of Department, Dept. of ECE, CEC and Asso. Prof. Ayoob Khan, Dept. of ECE, CEC.
Resource person being awarded certificate by Dr. Jyothiraj V.P., Head of Department,
Dept. of ECE, CEC and Asso. Prof. Ayoob Khan, Dept. of ECE, CEC.
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2017-8-11 2017-8-11 Europe/London One-Day Workshop on VLSI Design Flow One day workshop on “VLSI Design Flow” was organized by SSCS Chapter and IEDC Boot Camp College of Engineering Chengannur, India on 11th August 2017. The workshop was attended by B.Tech as well as PG students in the college. The aim of the programme was to introduce the participants to the world of VLSI design, College of Engineering, Chengannur
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